Flip Chip Challenges

Introduction Flip Chip packaging has seen an explosive growth in recent years. Over one billion devices a year are now assembled using flip chip technology. The majority are low lead count devices such as liquid crystal display drivers, watch modules, smart cards, and RFID tags. Recently the trend for higher I/O devices is to turn to flip chip in package (FCIP) as a packaging solution, which is the focus of this article. The growth in this area is driven by the needs of MPU’s and high speed and high frequency ASIC’s for the computing and communications market. The benefits of flip chip packaging include the following: • Flip chip technology overcomes wirebond pad pitch limitations, • Flip chip technology provides electrical designers with many advantages in the design of power and ground distribution on die, • Flip chip technology provides improved signal integrity for high speed or high frequency designs. Many MPU & ASIC customers have changed their interconnect technology from wire-bond to flip chip. Some of the most notable include AMD’s K6 and K7, Hewlett Packard’s PA-RISC, Motorola’s Power PC, Sun’s UltraSparc II, and Intel’s mobile and Coppermine MPU’s. Until recently, most of the flip chip activity has been relegated to these larger vertically integrated companies. The key to bringing flip chip to other types of companies is the availability of the logistical infrastructure for flip chip. Within the last two years, the scope of flip chip adopters has broadened to include non-vertically integrated and fabless companies as the support infrastructure has matured. As flip chip packaging expands, many choices are available to the customer such as various bumping technologies, substrate technologies, and the thermal management solutions. The assembler plays a key role in the selection process by providing a manufacturability and reliability viewpoint to this decision. Many challenges still need to be addressed as the market continues to push the limits of flip chip technology. This article will focus on high I/O FCIP devices by following the process flow for the assembly of a FCIP and discussing the challenges and tradeoffs related to selecting processes and materials.